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| 1-mbit (128k x 8) nvsram preliminary cy14b101l cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06400 rev. *e revised january 24, 2007 features ? 25 ns, 35 ns, and 45 ns access times ? ?hands-off? automatic store on power down with only a small capacitor ? store to quantumtrap tm nonvolatile elements is initiated by software, device pin, or autostore tm on power down ? recall to sram initiated by software or power up ?infinite read, write, and recall cycles ? 10 ma typical i cc at 200 ns cycle time ? 200,000 store cycles to quantum trap ? 20-year data retention @ 55 c ? single 3v operation +20 %, ?10% ? commercial and industrial temperature ? soic and ssop packages ? rohs compliance functional description the cypress cy14b101l is a fast static ram with a nonvolatile element in each memory cell. the embedded nonvolatile elements incorp orate quantumtrap technology producing, the world?s most reliable nonvolatile memory. the sram provides infinite read and write cycles; while independent, nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operati on) from the nonvolatile memory. both the store and recall operations are also available under software control. logic block diagram store/ recall control power control software detect static ram array 1024 x 1024 quantumtrap 1024 x 1024 store recall column io column dec row decoder input buffers oe ce we hsb v cc v cap a 15 - a 0 a 0 a 1 a 2 a 3 a 4 a 10 a 11 a 5 a 6 a 7 a 8 a 9 a 12 a 13 a 14 a 15 a 16 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 [+] feedback [+] feedback
cy14b101l preliminary document #: 001-06400 rev. *e page 2 of 18 pin configurations v cap a 16 a 14 a 12 a 7 a 6 a 5 a 4 v cc a 15 hsb we a 13 a 8 a 9 a 11 oe a 10 dq dq7 6 dq5 ce dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 nc nc nc nc v ss nc nc dq0 a 3 a 2 a 1 a 0 dq1 dq2 nc nc nc nc nc nc v ss nc nc v cc 48-ssop top view (not to scale) v cap a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 v ss v cc a 15 hsb we a 13 a 8 a 9 a 11 oe a 10 dq 7 dq 6 dq 5 ce dq 4 dq 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 23 22 21 20 19 18 17 27 26 25 24 28 32 31 30 29 32-soic to p vi e w (not to scale) [+] feedback [+] feedback cy14b101l preliminary document #: 001-06400 rev. *e page 3 of 18 device operation the cy14b101l nvsram is made up of two functional components paired in the same physical cell, the sram memory cell and the nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. transfer of data can be from the sram to the nonvolatile cell (the store operation), or from the nonvolatile cell to sram (the recall operation). this unique architecture allows all cells to be stored and recalled in parallel. during the store and recall operations sram read and write operations are inhibited. the cy14b101l supports infinite reads and writes just like a typical sram. in addition, it provides infinite recall operations from the nonvolatile cells and up to 200,000 store operations. sram read the cy14b101l performs a read cycle whenever ce and oe are low while we and hsb are high. the address specified on pins a 0-16 determines which of the 131,072 data bytes will be accessed. when the read is initiated by an address transition, the outputs will be valid after a delay of t aa (read cycle 1). if the read is initiated by ce or oe , the outputs will be valid at t ace or at t doe , whichever is later (read cycle 2). the data outputs repeatedly responds to address changes within the t aa access time without the need for transitions on any control input pins. it rema ins valid until another address change, or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed whenever ce and we are low and hsb is high. the address inputs must be stable before entering the write cycle and must remain stable until either ce or we goes high at the end of the cycle. the data on the common io pins io 0?7 will be written into the memory if the data is valid t sd before the end of a we controlled write or before the end of an ce controlled write. keep the oe high during the entire write cycle to avoid data bus contention on common io lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the cy14b101l stores data to nvsram using one of the three storage operations. these three operations are hardware store activated by hsb , software store activated by an address sequence, and autostore on device power down. autostore operation is a unique feature of quantumtrap technology and is enabled by default on the cy14b101l. during normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge will be used by the chip to perform a single store operation. if th e voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation will be initiated with power provided by the v cap capacitor. figure 1 on page 4 shows the proper connection of the storage capacitor (v cap ) for automatic store operation. refer to the dc characteristics table for the size of v cap . the voltage on the v cap pin is driven to 5v by a charge pump internal to the chip. a pull up must be placed on we to hold it inactive during power up. to reduce unnecessary nonvola tile stores, autostore, and hardware store operations will be ignored unless at least one write operation has taken place since the most recent store or recall cycle. soft ware initiated store cycles are performed regardless of whether a write operation has taken place. monitor the hsb signal by the syst em to detect if an autostore cycle is in progress. pin definitions pin name io type description a 0 ? a 16 input address inputs used to select one of the 131,072 bytes of the nvsram . dq0 ? dq7 input output bidirectional data io lines . used as input or output lines depending on operation. we input write enable input, active low . when selected low, enables data on the io pins to be written to the address location latched by the falling edge of ce . ce input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe input output enable, active low . the active low oe input enables the data output buffers during read cycles. io pins are tri-stated on deasserting oe high. v ss ground ground for the device. must be connected to ground of the system. v cc power supply power supply inputs to the device . hsb input output hardware store busy (hsb) . when low this output indicates a hardware store is in progress. when pulled low external to the chip it initiates a non volatile store operation. a weak internal pull up resistor keeps this pin high if not connected. (connection optional) v cap power supply autostore capacitor . supplies power to nvsram during power loss to store data from sram to nonvolatile elements. nc no connect no connect . do not connect this pin to the die. [+] feedback [+] feedback cy14b101l preliminary document #: 001-06400 rev. *e page 4 of 18 figure 1. autostore mode hardware store operation the cy14b101l provides the hsb pin for controlling and acknowledging the store operations. use the hsb pin to request a hardware store cycle. when the hsb pin is driven low, the cy14b101l conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram took place since t he last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the store (initiated by any means) is in progress. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the cy14b101l continues sram operations for t delay . during t delay , multiple sram r ead operations may take place. if a write is in progress when hsb is pulled low it will be allowed a time, t delay to complete. however, any sram write cycles requested after hsb goes low will be inhibited until hsb returns high. during any store operation, regardless of how it was initiated, the cy14b101l continues to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation the cy14b101l remains disabled until the hsb pin returns high. leave the hsb uncon- nected if is not used. hardware recall (power up) during power up or after any low power condition (v cc cy14b101l preliminary document #: 001-06400 rev. *e page 6 of 18 preventing autostore disable the autostore function by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initi- ation. to initiate the autostor e disable sequence, the following sequence of ce -controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable re-enable the autostore by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, the following sequence of ce -controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore function is disabled or re-enabled, a manual store operation (hardware or software) must be issued to save the autostore state through subsequent power down cycles. the part comes from the factory with autostore enabled. data protection the cy14b101l protects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc < v switch . if the cy14b101l is in a write mode (ce and we low) at power up after a recall, or after a store, the write will be inhibi ted until a negative transition on ce or we is detected. this protects against inadvert ent writes during power up or brownout conditions. noise considerations the cy14b101l is a high speed memory and so must have a high frequency bypass capacitor of approximately 0.1 f connected between v cc and v ss , using leads and traces that are as short as possible. as with all high speed cmos ics, careful routing of power, ground, and signals reduces circuit noise. low average active power cmos technology provides the cy14b101l the benefit of drawing less current when it is cycled at times longer than 50ns. figure 2 shows the relationship between i cc and read/write cycle time. worst case current consumption is shown for commercial temperature range v cc = 3.6v and chip enable at maximum frequency. only standby current is drawn when the chip is disabled. the overall average current drawn by the cy14b101l depends on the following items: 1. the duty cycle of chip enable. 2. the overall cycle rate for accesses. 3. the ratio of reads to writes. 4. the operating temperature. 5. the v cc level. 6. io loading. figure 2. current vs. cycle time [+] feedback [+] feedback cy14b101l preliminary document #: 001-06400 rev. *e page 7 of 18 maximum ratings exceeding maximum ratings may shorten the device battery life. these user guidelines are not tested. storage temperature .................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc relative to gnd .. ....... ?0.5v to 4.1v voltage applied to outputs in high-z state .......................................?0.5v to v cc + 0.5v input voltage ..........................................?0.5v to v cc + 0.5v transient voltage (<20 ns) on any pin to ground potential ..................?2.0v to v cc + 2.0v package power dissipation capability (t a = 25c) ................................................... 1.0w surface mount lead soldering temperature (three seconds) .................................... +260 c output short circuit current [4] .................................... 15 ma static discharge voltage.......................................... > 2001v (in accordance with mil-std-883, method 3015) latch up current.................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 2.7v to 3.6v industrial ?40 c to +85 c 2.7v to 3.6v dc electrical characteristics over the operating range (vcc = 2.7v to 3.6v) [5, 6, 7] parameter description test conditions min max unit i cc1 average v cc current t rc = 25 ns t rc = 35 ns t rc = 45 ns dependent on output loading and cycle rate. values obtained without output loads. i out = 0 ma. commercial 65 55 50 ma ma ma industrial 55 (t rc = 45 ns) ma i cc2 average v cc current during store all inputs do not care, v cc = max average current for duration t store 6ma i cc3 average v cc current at t aa = 200 ns, 3v, 25c typical we > (v cc ? 0.2). all other inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. i out = 0 ma. 10 ma i cc4 average v cap current during autostore cycle all inputs do not care, v cc = max average current for duration t store 3ma i sb v cc standby current we > (v cc ? 0.2). all others v in < 0.2v or > (v cc ? 0.2v). standby current level after n onvolatile cycle is complete. inputs are static. f = 0 mhz. 3ma i ix input leakage current v cc = max, v ss < v in < v cc ?1 +1 a i oz off state output leakage current v cc = max, v ss < v in < v cc , ce or oe > v ih ?1 +1 a v ih input high voltage [7] 2.0 vcc + 0.3 v v il input low voltage vss ? 0.5 0.8 v v oh output high voltage i out = ?2 ma 2.4 v v ol output low voltage i out = 4 ma 0.4 v v cap storage capacitor between v cap pin and v ss , 5v rated 17 120 f notes 4. outputs shorted for no more than one second. no more than one output shorted at a time. 5. typical conditions for the active current shown on the front page of the data sheet are average values at 25c (room temperat ure), and v cc = 3v. not 100% tested. 6. the hsb pin has i out = ?10 a for v oh of 2.4 v, this parameter is characterized but not tested. 7. v ih changes by 100 mv when v cc > 3.5v. [+] feedback [+] feedback cy14b101l preliminary document #: 001-06400 rev. *e page 8 of 18 capacitance [7] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0 v 7 pf c out output capacitance 7 pf thermal resistance [7] parameter description test co nditions 32-soic 48-ssop unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and proce- dures for measuring thermal impedance, in accordance with eia/jesd51. tbd tbd c/w jc thermal resistance (junction to case) tbd tbd c/w ac test loads ac test conditions input pulse levels.................................................. 0 v to 3 v input rise and fall times (10% ? 90%)....... ........... .... < 5 ns input and output timing reference levels................... 1.5 v 3.0v output 5 pf r1 577 ? r2 789 ? 3.0v output 30 pf r1 577 ? r2 789 ? for tri-state specs note 8. these parameters are guaranteed but not tested. [+] feedback [+] feedback cy14b101l preliminary document #: 001-06400 rev. *e page 9 of 18 ac switching characteristics parameter description 25 ns part 35 ns part 45 ns part unit min max min max min max cypress parameter alt. parameter sram read cycle t ace t acs chip enable access time 25 35 45 ns t rc [9] t rc read cycle time 25 35 45 ns t aa [10] t aa address access time 25 35 45 ns t doe t oe output enable to data valid 12 15 20 ns t oha t oh output hold after address change 3 3 3 ns t lzce [11] t lz chip enable to output active 3 3 3 ns t hzce [11] t hz chip disable to output inactive 10 13 15 ns t lzoe [11] t olz output enable to output active 0 0 0 ns t hzoe [11] t ohz output disable to output inactive 10 13 15 ns t pu [7] t pa chip enable to power active 0 0 0 ns t pd [7] t ps chip disable to power standby 25 35 45 ns sram write cycle t wc t wc write cycle time 25 35 45 ns t pwe t wp write pulse width 20 25 30 ns t sce t cw chip enable to end of write 20 25 30 ns t sd t dw data setup to end of write 10 12 15 ns t hd t dh data hold after end of write 0 0 0 ns t aw t aw address setup to end of write 20 25 30 ns t sa t as address setup to start of write 0 0 0 ns t ha t wr address hold after end of write 0 0 0 ns t hzwe [11, 12] t wz write enable to output disable 10 13 15 ns t lzwe [11] t ow output active after end of write 3 3 3 ns notes 9. we must be high during sram read cycles. 10. device is continuously selected with ce and oe low. 11. measured 200 mv from steady state output voltage. 12. if we is low when ce goes low, the outputs remain in the high impedance state. [+] feedback [+] feedback cy14b101l preliminary document #: 001-06400 rev. *e page 10 of 18 autostore/power up recall parameter description cy14b101l unit min max t hrecall [13] power up recall duration 20 ms t store [14, 15] store cycle duration 12.5 ms v switch low voltage trigger level 2.65 v t vccrise vcc rise time 150 s software controlled store/recall cycle [16, 17, 18] parameter description 25 ns part 35 ns part 45 ns part unit min max min max min max t rc store/recall initiation cycle time 25 35 45 ns t as address setup time 0 0 0 ns t cw clock pulse width 20 25 30 ns t ghax address hold time 1 1 1 ns t recall recall duration 50 50 50 s t ss [19, 20] soft sequence processing time 70 70 70 s hardware store cycle parameter description cy14b101l unit min max t delay [21] time allowed to complete sram cycle 1 70 s t hlhx hardware store pulse width 15 ns notes 13. t hrecall starts from the time v cc rises above v switch. 14. if an sram write has not taken place since the last nonvolatile cycle, no store takes place. 15. industrial grade devices require 15 ms max. 16. the software sequence is clocked with ce controlled or oe controlled reads. 17. the six consecutive addresses must be read in the order listed in the table 1, ?mode selection,? on page 5 . we must be high during all six consecutive cycles. 18. a 600 ? resistor must be connected to hsb to use the software command. 19. this is the amount of time it takes to take action on a soft sequence command. vcc power must remain high to effectively reg ister the command. 20. commands like store and recall lock out io until operation is comp lete, which further increases this time. see the specific command. 21. read and write cycles in progress before hsb are given this amount of time to complete. [+] feedback [+] feedback cy14b101l preliminary document #: 001-06400 rev. *e page 11 of 18 switching waveforms sram read cycle 1 (address controlled) [9, 10, 22] sram read cycle 2 (ce and oe controlled) [9, 22] t rc t aa t oha address dq (data out) data valid address t rc ce t ace t lzce t pd t hzce oe t doe t lzoe t hzoe data valid active standby t pu dq (data out) icc note 22. hsb must remain high during read and write cycles. [+] feedback [+] feedback cy14b101l preliminary document #: 001-06400 rev. *e page 12 of 18 sram write cycle 1 (we controlled) [22, 23] sram write cycle 2 (ce controlled) switching waveforms (continued) t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid note 23. ce or we must be > v ih during address transitions. [+] feedback [+] feedback cy14b101l preliminary document #: 001-06400 rev. *e page 13 of 18 figure 3. autostor e/power up recall figure 4. ce -controlled software store/recall cycle [17] switching waveforms (continued) v cc v switch t store t store t hrecall t hrecall autostore power-up recall read & write inhibited store occurs only if a sram write has happened no store occurs without atleast one sram write t vccrise a a t rc t rc t sa t sce t glax t store / t recall data valid data valid address # 1 address # 6 high impedance address ce oe dq (data) a a a a a a a a a a a a t ghax [+] feedback [+] feedback cy14b101l preliminary document #: 001-06400 rev. *e page 14 of 18 figure 5. oe -controlled software store/recall cycle [17] figure 6. hardware store cycle figure 7. soft sequence processing [19, 20] switching waveforms (continued) t rc t rc address # 1 address # 6 address t sa t sce t glax t store / t recall data valid data valid high impedance ce oe dq (data) a a a a a a a a a a a a a a t ghax t hlhx t store t hlbl t delay data valid data valid high impedance high impedance hsb (in) dq (data out) hsb (out) a a a a a a a a a a address # 1 address # 6 address # 1 address # 6 soft sequence command t ss 34 soft sequence command t ss 34 address v cc [+] feedback [+] feedback cy14b101l preliminary document #: 001-06400 rev. *e page 15 of 18 ordering information all of the following mentioned parts are of ?pb-free? type. sha ded areas contain advance information. contact your local cypres s sales representative for availability of these parts. speed (ns) ordering code package diagram package type operating range 25 CY14B101L-SZ25XCT 51-85127 32-pin soic commercial cy14b101l-sp25xct 51-85061 48-pin ssop 35 cy14b101l-sz35xct 51-85127 32-pin soic commercial cy14b101l-sp35xct 51-85061 48-pin ssop 45 cy14b101l-sz45xct 51-85127 32-pin soic commercial cy14b101l-sp45xct 51-85061 48-pin ssop 45 cy14b101l-sz45xit 51-85127 32-pin soic industrial cy14b101l-sp45xit 51-85061 48-pin ssop cy14b101l-sz45xi 51-85127 32-pin soic cy14b101l-sp45xi 51-85061 48-pin ssop option: t - tape & reel blank - std. speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns package: sz - 32 soic sp - 48 ssop data bus: l - x8 density: 101 - 1 mb voltage: b - 3.0v cypress part numbering nomenclature cy 14 b 101 l - sz 25 x c t nvsram 14 - autostore + software store + hardware store temperature: c - commercial (0 to 70c) i - industrial (?40 to 85c) pb-free [+] feedback [+] feedback cy14b101l preliminary document #: 001-06400 rev. *e page 16 of 18 package diagrams figure 8. 32-pin (300-mil) soic, 51-85127 pin 1 id seating plane 1 16 17 32 dimensions in inches[mm] min. max. 0.292[7.416] 0.299[7.594] 0.405[10.287] 0.419[10.642] 0.050[1.270] typ. 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.0100[0.254] 0.006[0.152] 0.012[0.304] 0.021[0.533] 0.041[1.041] 0.026[0.660] 0.032[0.812] 0.004[0.101] reference jedec mo-119 part # s32.3 standard pkg. sz32.3 lead free pkg. 0.014[0.355] 0.020[0.508] 0.810[20.574] 0.822[20.878] 51-85127-*a [+] feedback [+] feedback cy14b101l preliminary document #: 001-06400 rev. *e page 17 of 18 ? cypress semiconductor corporation, 2006-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems wh ere a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemni fies cypress against all charges. figure 9. 48-pin shrunk small outline package, 51-85061 autostore and quantumtrap are registered trademar ks of simtek corporation. all prod ucts and company names mentioned in this document are the trademar ks of their respective holders. package diagrams (continued) 51-85061-*c [+] feedback [+] feedback cy14b101l preliminary document #: 001-06400 rev. *e page 18 of 18 document history page document title: cy14b101l 1-mbit (128k x 8) nvsram document number: 001-06400 rev. ecn no. issue date orig. of change description of change ** 425138 see ecn tup new data sheet *a 437321 see ecn tup show data sheet on external web *b 471966 see ecn tup changed i cc3 from 5 ma to 10 ma changed isb from 2 ma to 3 ma changed v ih(min) from 2.2v to 2.0v changed t recall from 40 s to 50 s changed endurance from 1 million cycles to 500k cycles changed data retention from 100 years to 20 years added soft sequence processing time waveform updated part numbering nomenclature and ordering information *c 503272 see ecn pci changed from advance to preliminary changed the term ?unlimited? to ?infinite? changed endurance from 500k cycles to 200k cycles added temperature spec to data retention - 20 years at 55 c removed icc 1 values from the dc table for 25 ns and 35 ns industrial grade changed icc 2 value from 3 ma to 6 ma in the dc table added a footnote on v ih changed v switch(min) from 2.55v to 2.45v added footnote 17 related to using the software command updated part nomenclature table and ordering information table *d 597002 see ecn tup removed v switch(min) spec from the autostore/power up recall table changed t glax spec from 20 ns to 1 ns added t delay(max) spec of 70 s in the hardware store cycle table removed t hlbl specification changed t ss specification form 70 s (min) to 70 s (max) changed v cap(max) from 57 f to 120 f *e 688776 see ecn vkn added footnote related to hsb changed t glax to t ghax [+] feedback [+] feedback |
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